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Geschichte der Mikroprozessoren
Nur Intel-Prozessoren und Kompatible
| 1970 |
Intel
i4004 |
Der allererste Mikroprozessor. 4 bit data bus, 12 bit address bus (multiplexed).
Technology: PMOS. Die size: 24 mm2, 2250 transistors. |
| 1972 |
Intel
i4040 |
Intel i4004 CPU with extra features: more instructions, interrupt support. 4 bit data bus, 12 bit
address bus (multiplexed).
Technology: PMOS. |
Intel
i8008 |
8 bit data bus.16 bit address bus. April 1972.
Technology: PMOS. 3300 transistors. Used in Kenback-1. |
| 1973 |
Intel
i8080 |
8 bit data bus, 16 bit address bus. Data and address bus are multiplexed.
2 MHz, 2.67 MHz, 3.125 MHz.
Package: 40 pin CERDIP (CERamic Dual In-line Package).
Intel i8080 CPU: PMOS, 4500 transistors.
Intel i8080A CPU: NMOS, 4000 transistors. (8080A, 1976) |
| |
Zilog
Z80 |
Intel i8080
CPU upward instruction compatible. Not Intel i8080 CPU pin compatible (included: clock
generator).
2.5 MHz: NMOS.
4 MHz: NMOS.
6 MHz: NMOS.
8 MHz: NMOS.
10 MHz: CMOS.
Package: 40 pin CERDIP (CERamic Dual In-line Package). |
| 1976 |
Intel
i8085A
i8085AH |
Intel i8080
CPU upward instruction compatible. Extra instructions: SIM (Set Interrupt Mask), RIM (Read
Interrupt Mask). Extra interrupt lines, including NMI (Non-Maskable Interrupt). 8 bit data
bus, 16 bit address bus, Data and address bus are multiplexed.
Package: 40 pin CERDIP (CERamic Dual In-line Package). 6200 transistors.
3 MHz, 5 MHz, 6 MHz. |
| 1978 |
Intel
i8086A
i80C86A |
16 bit
internal data bus, 16 bit external data bus, 20 bit address bus.Data and address bus are
multiplexed. 1 Mbyte address space, 64 kbyte per segment.
4 MHz, 5 MHz, 8 MHz, 10 MHz, 12 Mhz.
Used in IBM PC clones, IBM PC/XT clones.
Package: 40 pin CERDIP (CERamic Dual In-line Package). 29E3 transistors. |
| 1979 |
Intel
i8088A
i80C88A |
16 bit
internal data bus, 8 bit external data bus (can co-operate with all Intel i8085 CPU
periphery chips). 20 bit address bus. Data and address bus are multiplexed. 1 Mbyte
address space, 64 kbyte per segment.
5 MHz, 8 MHz, 10 MHz, 12 MHz.
Package: 40 pin CERDIP (CERamic Dual In-line Package).
Used in IBM PC and IBM PC/XT.
Nachbauten von AMD, Harris, Siemens. |
| 1983 |
Intel
80186/
80C186
80188/
80C188 |
Intel i8086
CPU / Intel i8088 CPU with extra features. |
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NEC
V20 |
Intel i8088
CPU pin compatible, Intel i80188 CPU upward instruction compatible.
Extra features: extra instructions: BCD, Intel i8080 CPU simulation, fewer CPI (Cycles Per
Instruction).
8 MHz, 10 MHz: $10. Also made by Sony under license from NEC. |
| |
NEC
V30 |
Intel i8086
CPU pin compatible. Intel i80186 CPU upward instruction compatible.
Extra features: extra instructions: BCD, Intel i8080 CPU simulation, fewer CPI (Cycles Per
Instruction). 10 MHz: $10.
Intel i80886 (?) |
| 1982 |
Intel
i80286 |
Real mode:
Intel i8086/i8088 CPU mode.
Protected mode: 16 MByte address space, 64 kbyte per segment, 1 Gbyte virtual memory. 16
bit data bus, 24 bit address bus.
6 MHz, 8 MHz, 10 MHz, 12 MHz, 16 MHz, 20 MHz.
Package: 68 pin CERDIP (CERamic Dual In-line Package).
Used in IBM PC/AT.
Technology: HMOS. 134E3 transistors.
Nachbauten von AMD, Harris, Siemens. |
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Intel
i80386
(all modells) |
All
modells:
Real mode: Intel i8086/i8088 CPU mode.
Protected mode: 64 Tbyte virtual memory, 4 Gbyte per segment.
Virtual 8086 mode (V86 mode): parallel simulation of more virtual Intel i8086/i8088 CPU's.
POPAD bug: EAX register is trashed when there is a memory access instruction directly
after the POPAD instruction. |
| October
1985 |
Intel
i80386
i80386DX |
32 bit
internal data bus, 32 bit external data bus (DX: Double-word eXternal), 32 bit address
bus.
12 MHz: first 16 MHz CPU's had clock speed troubles and were released as 12 MHz items.
16 MHz: early Intel i80386 CPU's had a bug in the 32 bit MUL instruction (MUL bug); it is
fixed in the double-sigma step level, no longer available.
20 MHz, 25 MHz, 33 MHz.
Package: 132 pin PGA (Pin Grid Array).
Technology: CMOS. 275.000 transistors. |
| June 1988 |
Intel
i80386SX |
32 bit
internal data bus, 16 bit external data bus (SX: Single-word eXternal). 24 bit address
bus.
16 MHz, 20 MHz, 25 MHz, 33 MHz.
Package: 100 pin QFP (Quad Flat Package).
Technology: CMOS. |
| October
1990 |
Intel
i80386SL |
Low power
version of the Intel i80386SX CPU: SMM (System Management Mode) Static core. Extra pins
assigned for power management. Extra features: PI-bus (Peripheral Interface), cache
controller, tag RAM, MCU (Memory Control Unit), ISA-bus driver (Industry Standard
Architecture). Intel i80386SX CPU upward pin compatible.
16 MHz, 20 MHz, 25 MHz, 33 MHz.
Technology: CMOS. |
Quellen: u.a.:
CHIP LIST 5.0 by Aad Offerman, 27-06-94, 3137NE Vlaardingen The Netherlands,
auf rtfm.mit.edu pub/usenet/news.answers/pc-hardware-faq/chiplist/ |
